Military

Aldec offers finite state machine coverage for verification of safety-critical FPGAs

HENDERSON, Nev. Aldec Inc. is introducing the latest version of its mixed-language, field-programmable gate array (FPGA) design and simulation platform, Active-HDL 10.4, providing finite-state machine ...
Business Wire

Aldec Adds Customizable Tool Qualification Data Package to ALINT-PRO™ for DO-254 Projects

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has added a customizable tool qualification data ...
Electronic Design

EDA Update: Mixed HDL/C-Language Design For FPGAs

Mixed HDL/C-Language design for FPGAs recently debuted, courtesy of Aldec Inc. and Celoxica Ltd. The Active-HDL+C integrated FPGA design environment combines Aldec's Active-HDL design entry and ...
Business Wire

Aldec Launches HES-DVM Proto ‘Cloud Edition’ - Giving Engineers Easier Access to FPGA-based ASIC & SoC Prototyping

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has launched HES-DVM Proto Cloud Edition (CE).