EDN

VHDL program enables PCI-bus-arbiter core

This Design Idea describes a VHDL implementation of a PCI 2.2-bus arbiter (Figure 1). Any PCI system may have one or more PCI-master devices. Most devices can behave as target hosts, but one must be a ...
EDN

Intel discloses ‘arbiter’ bus with revised 64-bit processor line

SAN FRANCISCO — Intel Corp. has disclosed more details of its revamped road map for 64-bit microprocessors, including some key specifications for its long-awaited Madison and Montecito chips for ...
Design-Reuse

Performance verification of a complex bus arbiter using the VMM Performance Analyzer

Kelly Larson, John Dickol and Kari O’Brien, MediaTek Wireless, Inc. Performance verification of system bus fabrics is an increasingly complex problem. The bus fabrics themselves are growing in ...