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Samsung touts 96% lower-power NAND design — researchers investigate design based on ferroelectric transistors

Samsung researchers have published a detailed account of an experimental NAND architecture that aims to cut one of the technology’s largest power drains by as much as 96%. The work — Ferroelectric ...
EDN

Flip-Flop Using CMOS NAND Gates

Using just two NAND or inverter gates its possible to build a D type (or ‘toggle’) flip-flop with a push-button input. At power-up the output of gate N2 is at a logical ‘1’, ensuring that transistor T2 ...
Ars Technica

Samsung’s “3D Vertical” NAND crams a terabit on a single chip

SSD enthusiasts know all about SLC, MLC, and TLC, but there are some new acronyms in SSD town: V-NAND and CTF. Samsung announced in a press release last night that it has begun mass production of “3D ...
EDN

Samsung Electronics Develops First 16-Gigabit NAND Memory Using 50-nm Technology for Sharp Jump in Mobile Storage CapacitySamsung Electronics Develops First 16-Gigabit NAND Memory

Samsung Electronics Develops First 16-Gigabit NAND Memory Using 50-nm Technology for Sharp Jump in Mobile Storage CapacitySamsung Electronics Develops First 16-Gigabit NAND Memory Samsung Electronics ...
Forbes

IMFT: Intel's Billion-Dollar Sandbox

It's getting increasingly expensive to continue along the chip trajectory predicted by Moore's Law, the observation that the number of transistors on a chip doubles every year or two. One way that ...