Electronic Design

Don’t Do It: Ignore Worst-Case Execution Time

WCET analysis is essential for proving multicore real-time systems meet safety-critical deadlines under all operating ...
Yahoo Finance

TASKING Delivers Advanced Worst-Case Timing Coupling Analysis and Mitigation for Multicore Designs

The enhanced TASKING integrated toolchain combines compile, debug, and test capabilities to automate the measurement, assessment, and optimization of hidden timing interference in multicore SoCs for ...
EDN

Timing Closure Using Layout Based Design Process

Chung-Kuan Cheng received a Ph.D. degree inelectrical engineering and computer sciences from University ofCalifornia, Berkeley in 1984. From 1984 to 1986 he was a senior CADengineer at Advanced Micro ...
Electronic Design

A Holistic Approach to Meet Multicore-System Timing and Interference Requirements

How to apply CAST-32A and A(M)C20-193 guidance for heterogeneous multicore processors. Techniques for measuring timing and interference on heterogeneous multicore processors. How to employ robust ...
Semiconductor Engineering

Using Virtual Metal Fill To Predict The Impact Of High Level Nets

A recent blog post discussed the use of virtual metal fill (VMF) to predict the effects of real metal fill when performing RC extraction on a chip layout. This enables static timing analysis (STA) ...
New Electronics

TASKING unveils enhanced timing analysis tools for multicore embedded systems

TASKING has unveiled new upgrades to its unified development toolchain aimed at improving worst‑case timing and coupling analysis for real‑time multicore embedded systems used in safety‑critical ...