EDN

Using complex triggers in an FPGA-based RTL debugger

When a design is simulated, the level of verification is a function of how accurately the simulation vectors mimic the operating environment. Designs that are simulated with vectors that accurately ...
Hackaday

X-Ray Vision For FPGAs: Using Verifla

Last time I talked about how I took the open source Verifla logic analyzer and modified it to have some extra features. As promised, this time I want to show it in action, so you can incorporate it ...
EDN

Debugging hybrid FPGA logic/processor designs

FPGAs continue to advance, enabling ever more integration of programmable technologies into the heart of embedded systems. Today’s high-performance FPGAs boast hundreds of thousands of programmable ...
Design-Reuse

Algo-Logic Systems Launches Third Generation FPGA Accelerated CME Tick-To-Trade System

SANTA CLARA, Calif., May. 10, 2017 – Algo-Logic Systems announces the release of their third generation Field Programmable Gate Array (FPGA) accelerated CME Group (CME, CBOT, COMEX, and NYMEX) Tick-To ...
Design-Reuse

Using complex triggers in an FPGA-based RTL debugger

When a design is simulated, the level of verification is a function of how accurately the simulation vectors mimic the operating environment. Designs that are simulated with vectors that accurately ...